- In a 12-month senior design project, I created JTAG testing interface for Cortex-M0, applied logic encryption of digital circuits and physically implemented the chip in Synopsys suite
Applying chip design strategies for fabless world
Integrated circuit production facilities cost US$1+ billion, which is why semiconductor companies are shifting into a more effective “fabless” model. Chip designers now create floorplans, but do not manufacture the chips in-house. Instead, external foundries produce the chip. The purpose of the capstone project was to conduct implementation from the register transfer level to GDSII, while addressing concerns that arise from fabrication outsourcing.
Our design process paralleled research of NYUAD’s Design for Excellence group, shown in the video below.
Testability, encryption and physical implementation as best practices
As most chip foundries offer mutually substitutable services, the intellectual property is the core value driver in the industry. Thus, the project focused on integrating new functionalities with an existing design of an ARM Cortex-M0 chip, instead of starting the chip creation process bottom-up. To ensure testability after manufacturing, Cortex-M0 netlist was enriched with a JTAG module for functional and scan chain testing.Additionally, providing the chip design to untrusted foundries raises concerns about illegal chip printing and tampering. SAT Attack Resistant Logic Locking (SARLock) logic encryption method was applied to prevent overproduction and insertion of Trojans. Lastly, chip printing is expensive, and the foundry only accepts new designs at specific dates, so a mistake in physical implementation can be costly and lead to major delays. Therefore, rigorous physical implementation was performed.